1. Field of the Invention
The present invention relates to a method of manufacturing an electrically programmable non-volatile semiconductor memory device. More particularly, it relates to a method of manufacturing a non-volatile semiconductor memory device with a threshold voltage which is controlled by impurity implantation in a channel region.
2. Description of the Related Art
In recent years, there has been much activity in development of flash EEPROMs. There are now mainly two types of flash memory EEPROMs. One is the floating gate type flash EEPROM, which can erase and program data by controlling the charge stored in a floating gate formed between a gate insulating layer and a controlling gate via an insulating layer.
The other is the metal-oxide-nitride-oxide-semiconductor (MONOS) type flash EEPROM, which can erase and program data by controlling the charge stored in a gate insulating layer including a nitride layer.
Further, flash EEPROMs may be classified by the arrangement of the memory cell or the means for programming into a common-source, parallel-array type (NOR type), a separate-source, parallel-array type (AND type), a series type (NAND type), a divided-bit-line, parallel array type (DINOR type), and so on.
A flash memory requires implantation of impurities into a channel region in order to control the threshold voltage or to make a depletion mode transistor. However, the impurities doped in the channel region are re-diffused by the heating process after forming the gate insulating layer, so the profile of the impurities is modified. This prevents the fabrication of high density memory devices.
A MONOS type flash memory, in particular, requires a depletion mode transistor, so punch through occurs easily and makes fabrication of a high density memory device difficult.
An object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory device which can maintain its impurity profile in its channel region and therefore enables fabrication of a high density memory device.
According to one aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device having a gate insulating layer composed of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer and a gate electrode, comprising the steps of forming the gate insulating layer on a semiconductor substrate, introducing an impurity into a channel region of the semiconductor substrate after forming the gate insulating layer, and forming a gate electrode on the gate insulating layer.
According to another aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device having a gate insulating layer composed of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer and a gate electrode, comprising the steps of forming the gate insulating layer on a semiconductor substrate, forming a polycrystalline silicon layer composed of the gate electrode on the gate insulating layer, and introducing an impurity into a channel region of the semiconductor substrate after forming the polycrystalline silicon layer.